Logic and Bit

Logic

While wire and reg are Verilog data types, logic type introduced in SystemVerilog is the universal data type that has taken precedence over the older reg and wire types. It's part of SystemVerilog's move towards unifying the data type system.

A logic in SystemVerilog is essentially a 4-state data type. The four states are 0, 1, X, and Z.

In terms of declaration and usage, logic acts just like reg type. It can hold a value and you can write procedural assignments to it, similar to variables in other languages:

logic my_signal;
initial begin
    my_signal = 1'b0;
    #10;
    my_signal = 1'b1;
end

logic can also be used in continuous assignments simiar to wire:

module my_module(input logic clk, output logic out_signal);
    // Module body
endmodule

logic type is a versatile, universal data type in SystemVerilog, fit for both combinational and sequential logic, offering a clean and consistent way to model digital circuits.

SystemVerilog introduced the 'logic' type, which can behave both as 'wire' (can be driven by continuous assignments and ports) and as 'reg' (can hold a value and can be driven by procedural assignments). 'bit' is another data type similar to 'logic', but it can hold only binary values 0 and 1.

Bit

In SystemVerilog, the bit data type is a two-state data type, meaning it can only take on values of 0 or 1. This makes it distinct from the 4-state SystemVerilog logic types (logic, wire, reg, etc.) that can take on the values 0, 1, X (unknown), and Z (high impedance).

module bit_example; bit [3:0] four_bit_binary = 4'b1010;

initial begin
    four_bit_binary = four_bit_binary + 1;
    $display("Value of four_bit_binary: %0d", four_bit_binary);
end

endmodule

bit is a data type similar to logic, but it can hold only binary values 0 and 1 while logic can hold 4 state values (0, 1, x, z).