Modules and Ports

In SystemVerilog, the most basic design entity is a module. It's akin to a building block, and complex digital systems are created by combining these modules in various configurations. Each module serves a particular purpose and is independent of the others.

Let's start by defining a simple module.

Defining a Module

The definition of a module begins with the keyword 'module', followed by the module name, a list of ports in parentheses, and then the keyword 'endmodule'.

For example:

module MyModule;
// Module contents go here
endmodule

In this case, MyModule is a module with no ports.

Adding Ports

Ports are the communication interfaces for a module. They allow signals to be passed in and out of the module. There are three types of ports: input, output, and inout.

Let's add an input and an output port to the MyModule.

module MyModule(
    input wire inSignal,
    output wire outSignal
);
// Module contents go here
endmodule

In this case, inSignal is an input port, and outSignal is an output port. The 'wire' keyword declares the port as a wire data type.

Ports Direction and Type

Input ports are used to bring signals into the module, and output ports are used to take signals out of the module. The inout port can act as both an input and an output, but it's less commonly used.

Ports can also be declared with different data types like 'wire', 'reg', 'logic', 'int', 'real', etc. The 'wire' data type is used for connection paths and typically for inputs and outputs. The 'reg' and 'logic' types are used for variables that hold state and are typically used inside the module.

That's it for this tutorial on modules and ports. In the next tutorial, we'll delve into the data types and their usage in SystemVerilog. Please note that this is a simplistic explanation for beginners and the real-world usage can be more complex with the use of different data types for ports, use of arrays, structs, unions, etc.