Printing and Displaying Output

Being able to print or display output is a fundamental capability in any programming or scripting language. This functionality enables debugging, demonstrates simulation results, and offers valuable feedback. In SystemVerilog, the $display system task is frequently used for printing

$display System Task

The $display system task allows you to print formatted output to the standard output, usually your console or terminal. The task works similarly to the printf function found in the C programming language.

Here's the syntax for $display:

$display(format_string, list_of_arguments);

The format_string represents the text to be outputted, which can include format specifiers for variables. The list_of_arguments encompasses the variables to be printed, which correspond to the format specifiers in the format_string.

One key feature of the $display function is that it automatically appends a newline character at the end of its output, which means each $display call will output on a new line.

Consider the following example:

module MyModule;
    integer a = 10;
    integer b = 20;
    initial begin
        $display("The values of a and b are %d and %d respectively.", a, b);
    end
endmodule

Output:

The values of a and b are 10 and 20 respectively.

In this example, the values of a and b will replace the %d format specifiers in the format_string, resulting in the output: "The values of a and b are 10 and 20 respectively."

Format Specifiers

Format specifiers determine the format of the variable values in the output. Some common format specifiers in SystemVerilog include:

• %d or %0d: For decimal integer

• %b: For binary

• %h: For hexadecimal

• %o: For octal

• %s: For string

• %f: For real numbers

These specifiers can be used within the format_string in the $display task. For instance:

module MyModule;
    integer a = 10;
    real b = 20.5;
    initial begin
        $display("In decimal: a = %d, b = %f", a, b);
        $display("In hexadecimal: a = %h", a);
        $display("In binary: a = %b", a);
    end
endmodule

Output:

In decimal: a = 10, b = 20.500000
In hexadecimal: a = A
In binary: a = 1010

The $display system task is essential in SystemVerilog programming. As you continue with this tutorial series, you will frequently use $display to print output and debug your code. Always remember the proper use of format specifiers to represent different types of variables in your output.