Int and Real

Int

In SystemVerilog, integers play an essential role in both design and verification environments. These are used to represent whole numbers, both positive and negative.

int represents a 32-bit signed integer. It can hold values from -2,147,483,648 to 2,147,483,647.

int counterA = -100;
int counterB = 100;

In SystemVerilog, int is a 4-state, 32-bit two's complement signed integer, introduced as a part of SystemVerilog enhancements, ensuring consistent size and behavior across tools. On the other hand, integer is a legacy Verilog type that is typically 32-bit and 4-state. For modern SystemVerilog code, using int is generally recommended.

Real

In SystemVerilog, the real data type represents floating-point numbers. These numbers can have a fractional component, and they are essential for modeling and verifying systems where precise value representations are needed, such as in analog or mixed-signal environments.

real LDO_voltage = 3.3;
real BIAS_current = 0.015;