Coverage

Coverage is a vital part of the verification process. The goal of verification is to ensure that the design is correct and meets all the requirements, but it's also to ensure that all aspects of the design have been tested. Coverage is a metric that measures the extent to which our verification environment has tested our design. Essentially, it helps us answer the question, "How much of our design have we tested?"

Coverage in SystemVerilog can be broadly divided into the following types:

1. Code Coverage: Code coverage helps to measure how much of the RTL code (written in hardware description languages like Verilog or VHDL) has been executed by our tests. This includes line coverage, toggle coverage, condition coverage, etc.

2. Functional Coverage: Functional coverage is defined by the user and measures how much of the design specification has been covered by the tests. It is used to ensure that all functionality of the design has been checked. SystemVerilog provides constructs like covergroups, coverpoints and crosses to capture functional coverage.

3. Assertion Coverage: This measures how much of the assertions in the design have been hit during verification. Assertions are often used to check properties of the design, and they should be checked during the verification process.