Assignments

Assignments are fundamental to creating meaningful logic in your SystemVerilog designs. Two key types of assignments that SystemVerilog employs are Continuous Assignments and Procedural Assignments.

Continuous Assignments

Continuous Assignments are used to continuously drive values onto nets (wire, tri, wor, triand, trior, trireg). The assign keyword is used to initiate a continuous assignment.

In a continuous assignment, any change in the right-hand-side (RHS) expression immediately causes a new value to be computed and assigned to the left-hand-side (LHS). This mimics the behavior of hardware where the output of a gate immediately changes upon any change in its input.

Here's an example:

module MyModule;
    wire a;
    assign a = 1'b0; // a is continuously assigned the value 0
endmodule

In this example, a is assigned a value of 1'b0 continuously. Whenever simulation time advances, a would still hold 1'b0.

Procedural Assignments

Procedural Assignments occur within procedural blocks such as initial, always, task, or function. Procedural assignments assign values to variables (reg, integer, time, real, realtime, logic) or nets (trireg).

In procedural assignments, assignments are executed in the order they appear in the procedural block and they happen only when control flow reaches the assignment statement.

Here's an example:

module MyModule;
    reg a;
    initial begin
        a = 1'b0; // a is assigned the value 0 at the start of the simulation
        #10 a = 1'b1; // a is assigned the value 1 after 10 time units
    end
endmodule

In this example, a is assigned a value of 1'b0 at the start of the simulation. After 10 time units, a is reassigned the value 1'b1.

In conclusion, Continuous Assignments are essential for defining the continuous behavior of digital circuits, much like physical hardware. On the other hand, Procedural Assignments help define the sequence of operations, model stateful elements, or express complex logic that changes with time. Understanding the difference is crucial for correct and efficient hardware designs in SystemVerilog.