System Task and Functions

Built-in or pre-defined tasks and function in SystemVerilog

In this section, we will be focusing on system tasks and functions.

System Tasks and Function built into the language where as User-Defined tasks and functions are defined by the user.

System tasks and functions are utilized for various purposes, including but not limited to displaying messages, reading and writing files, controlling simulation, and more. Let's delve into some of the most commonly used system tasks and functions:

$display and $write System Tasks

As we discussed in an earlier tutorial, $display system tasks are used for printing formatted text to the console. The $display task adds a newline at the end of the output, while $write does not.

module MyModule;
    integer a = 10, b = 20;
    initial begin
        $display("The values of a and b are %d and %d respectively.", a, b);
    end
endmodule

In this example, the output will be "The values of a and b are 10 and 20 respectively."

$finish and $stop System Tasks

The $finish and $stop system tasks are used to control the simulation run. $finish ends the simulation immediately, while $stop pauses the simulation, allowing you to resume it later if desired.

module MyModule;
    initial begin
        $display("Starting simulation");
        // some code
        $finish;
    end
endmodule

In this example, the $finish task ends the simulation after the message is displayed and the intermediate code (if present) is executed.

$time and $realtime System Function

The $time system function is used to obtain the current simulation time.

module MyModule;
    initial begin
        #10; // delay of 10 time units
        $display("The current time is %0d", $time);
    end
endmodule

In this example, after a delay of 10 time units, the current simulation time is displayed.

module MyModule;
    initial begin
        #10.5; // delay of 10.5 time units
        $display("The current time is %0f", $realtime);
    end
endmodule

In this example, after a delay of 10.5 time units, the current simulation time is displayed.

$time returns the current simulation time as an integer, while $realtime provides the simulation time as a decimal, useful for high precision and mixed-signal simulations.

Remember, system tasks and functions are part of the SystemVerilog language itself and provide standard functionality. On the other hand, user-defined tasks and functions, which we will cover in a future tutorial, offer the ability to create custom, reusable pieces of code to perform specific operations that are not directly available as system tasks or functions. It's important to understand the distinction and the appropriate use cases for each. As you continue to explore and learn SystemVerilog, you'll gain more hands-on experience and insights into how to effectively use both system and user-defined tasks and functions.

A complete list of all SystemVerilog tasks and function can be found in the appendix section.

System Tasks and functions can only be placed inside procedural context. There they can go inside a initial, always, task and function.

Building on from the last tutorial, here is a diagram showing where you can call system tasks and functions.