Wire and Reg

Wire

In SystemVerilog, the wire data type represents physical wires or connections in hardware. A wire does not store a value but merely acts as a conduit to propagate it from one point in the design to another.

Characteristics and Usage:

1. 4-State: Wires in SystemVerilog can be in one of four states: 0, 1, X (unknown), or Z (high-impedance). This capability allows for more accurate modeling of real-world electronic behaviors.

2. Continuous Assignments: Wires are typically used with continuous assignments. When the right-hand side (RHS) of a continuous assignment changes, the new value is immediately driven onto the wire.

   wire a;
   assign a = b & c;  // b and c are inputs

   In the example above, the value of a will change whenever b or c changes.

3. Ports: Wires can be used for input and inout ports of modules. The values driven onto a wire can come from continuous assignments or from ports of instantiated modules.

4. No Storage: Unlike variables (like reg or int), a wire does not store a value. It's essentially a conduit that connects parts of your design.

5. Driven by Only One Source: A wire should only be driven by one source. Having multiple drivers for a single wire will lead to contention and result in an unknown value (X) on the wire.

Reg

In SystemVerilog, the reg type is not indicative of hardware registers but rather symbolizes a data object capable of holding a value across different simulation time steps. Its name might initially mislead beginners, but its primary use is to store a value for procedural assignments, typically inside procedural blocks.

Characteristics and Usage:

1. 4-State Value: The reg data type in SystemVerilog can take on one of four states: 0, 1, X (unknown), or Z (high-impedance). This four-state capability models the uncertainties often encountered in digital logic simulations.

2. Procedural Assignments: Unlike the wire which takes its value from continuous assignments, the reg type gets its value from procedural assignments, commonly within always, initial, task, or function blocks.

   reg my_reg;
   always @(posedge clk) 
       my_reg <= input1 & input2;
   
   initial begin
       my_reg = 1'b0; // initialization of reg
   end

   Here, my_reg will be assigned a new value with every positive edge of the clk signal. The initial block ensures that my_reg starts with a known value at the beginning of the simulation.

3. Multiple Assignments: A reg can be assigned multiple times within a procedural block, but it retains the value of the last assignment after the block completes.

   reg r;
   initial begin
       r = 1'b0;
       #10 r = 1'b1;
       #20 r = 1'b0;
   end

   In this example, the value of r changes over time during the simulation.

4. Array Declaration: reg data types can also be used to declare arrays. This feature is useful for handling vector signals and storing multiple values.

5. Module Ports: Although the reg data type can connect to module ports, it cannot be declared as an input port directly. It is, however, valid for output and inout.

6. Storage Properties: Unlike wire, the reg data type can hold and remember its value between simulation time steps.

The reg data type's nuances in SystemVerilog are foundational. Its proper understanding and application are pivotal for accurate simulations and can preempt potential pitfalls in design or verification phases.

A wire is a physical connection typically driven by a continuous assignment (assignstatement) or a module output, while a reg represents a storage element and can be driven within procedural code blocks like always or initial.