Operators and Expressions

Arithmetic Operators

SystemVerilog supports basic arithmetic operators, including addition (+), subtraction (-), multiplication (*), division (/), and modulus (%). The modulus operator gives the remainder of a division operation.

Example:

module MyModule;
    integer a = 10;
    integer b = 20;
    integer c = a + b; // c is 30
    integer d = a * b; // d is 200
    integer e = a % b; // e is 10, because 10 divided by 20 gives a remainder of 10
// Module contents go here
endmodule

Bitwise Operators

Bitwise operators perform operations on the binary representations of values. They include bitwise AND (&), OR (|), XOR (^), NOR (|), XNOR (^ or ^), NOT (), and binary shifts (<< and >>).

Example:

module MyModule;
    logic [7:0] a = 8'b10101010;
    logic [7:0] b = 8'b01010101;
    logic [7:0] c = a & b; // c is 8'b00000000
    logic [7:0] d = a | b; // d is 8'b11111111
    logic [7:0] e = a ^ b; // e is 8'b11111111
    logic [7:0] f = ~a;    // f is 8'b01010101
    logic [7:0] g = a << 2;// g is 8'b10101000
    logic [7:0] h = b >> 1;// h is 8'b00101010
// Module contents go here
endmodule

Logical Operators

Logical operators are used for Boolean algebra and include logical AND (&&), OR (||), and NOT (!).

Example:

module MyModule;
    logic a = 1'b1;
    logic b = 1'b0;
    logic c = a && b; // c is 1'b0
    logic d = a || b; // d is 1'b1
// Module contents go here
endmodule

Relational and Equality Operators

Relational operators are used to compare values and include greater than (>), less than (<), greater than or equal to (>=), and less than or equal to (<=). Equality operators are used to check the equality or inequality of values and include equality (==), inequality (!=), case equality (===), and case inequality (!==).

The equality operators (== and !=) are used for logical comparison, meaning that X and Z values are treated as unknowns and may cause the result to be X (unknown). On the other hand, the case equality operators (=== and !==) are used for bitwise comparison, meaning that X and Z values are treated as valid values.

Example:

module MyModule;
    integer a = 10;
    integer b = 20;
    logic c = a == b; // c is 1'b0
    logic d = a < b;  // d is 1'b1

    logic [7:0] x = 8'b1001_XXXX;
    logic [7:0] y = 8'b1001_0000;
    logic e = (x == y);  // e is 1'bX (unknown), because == can't handle 'X'
    logic f = (x === y); // f is 1'b0 (false), because === treats 'X' as a valid value
// Module contents go here
endmodule

I hope this more comprehensive exploration of operators helps clarify their usage in SystemVerilog. In the next tutorial, we'll delve into control flow constructs. As always, remember that this is a simplified explanation for beginners, and real-world usage might involve more complex expressions and combinations of these operators.