Procedural Assignments

Procedural Assignments are a central aspect of SystemVerilog that are used to define the behavior of variables within procedural blocks such as initial, always, task, and function. These types of assignments differ significantly from Continuous Assignments as they are executed sequentially, following the flow of control in the procedural block, and not instantly upon changes to dependent variables.

Let's dive a bit deeper into this concept.

Procedural assignments are typically employed on data objects of type reg, integer, real, realtime, time, and logic. They also apply to certain net types like trireg. Unlike continuous assignments that can operate outside of any procedural block, procedural assignments occur within procedural blocks and follow a specific control flow, much like traditional software programming languages.

Here's a simple example:

module MyModule;
    logic a;
    initial begin
        a = 1'b0;
        #10 a = 1'b1;
    end
endmodule

In this example, the initial block starts executing at the beginning of simulation. The variable a is first assigned the value 0 at time 0. Then, after a delay of 10 time units (expressed with #10), a is reassigned the value 1. It's important to note that the simulation would wait for 10 time units before reassigning a, unlike continuous assignments that instantly propagate changes.

Procedural assignments can come in two forms: blocking (=) and non-blocking (<=). A blocking assignment (=) will not allow the execution to proceed until the assignment has been completed. On the other hand, a non-blocking assignment (<=) schedules the assignment to occur at the end of the current time step and allows the execution to continue with the next statement without waiting for the assignment.

Blocking assignment example:

module MyModule;
    reg a, b;
    initial begin
        a = 1'b0;
        b = a;
    end
endmodule

In this example, b will be assigned the value of a right after a gets the value 0, meaning b will also be 0.

Non-blocking assignment example:

module MyModule;
    reg a, b;
    initial begin
        a <= 1'b0;
        b = a;
    end
endmodule

In this example, b will not get the updated value of a immediately as the assignment of a is non-blocking. If a had a value before the initial block (for example, 1), b would be assigned that previous value.

Blocking Assignments (=): The execution of the next statement is blocked until the current assignment statement completes. They are used when the order of execution is important, such as in sequential logic.

Non-Blocking Assignments (<=): The assignment doesn't block the execution of subsequent statements. All non-blocking assignments are evaluated concurrently at the beginning of the time step, and their assignments occur at the end of the time step. They're typically used to model concurrent behavior, such as in flip-flops or latches where multiple outputs change simultaneously.

Procedural assignments, particularly with the concept of blocking and non-blocking assignments, are key to modeling sequential logic elements like flip-flops and registers and to correctly implement sequential procedural behaviors. A deep understanding of these principles is critical for effective use of SystemVerilog for digital design.