Continuous Assignments

In SystemVerilog, Continuous Assignments are a fundamental way to model the behavior of digital circuits at a low level. They closely mirror how hardware systems function, where signals propagate through wires and gates spontaneously, without requiring a clock tick or control flow.

Continuous Assignments are primarily associated with the wire and logic data types in SystemVerilog, along with other net types (tri, wor, triand, trior, trireg).

Assign Statement

The assign keyword is used to initiate a continuous assignment.

Here's the basic syntax for a continuous assignment:

assign target = expression;

In this, target is a wire or logic type variable, and expression can be any combinational logic formula using logic operators and other wires, logic, or reg variables.

For example:

module MyModule;
    logic x, y, z;
    assign x = 1'b0;
    assign y = ~x;
    assign z = x | y;
endmodule

In this example, x is continuously assigned the value 0. Consequently, y gets the value 1 as it is continuously assigned the bitwise NOT of x . z is assigned the logical OR of x and y, and thus, it also gets the value 1.

The unique aspect of continuous assignments is their reactivity. If the value of a variable in the right-hand-side (RHS) changes, the expression is re-evaluated instantaneously, and the new result is driven onto the target. This behavior is indicative of the actual operation of digital hardware circuits.

Continuous assignments exist outside procedural blocks, making them concurrent in nature, in contrast to procedural assignments which are sequential and dependent on their order inside procedural blocks.

One crucial point to remember is that assigning more than one continuous assignment to the same wire or logic leads to a conflict. SystemVerilog will resolve this using a resolution function, but it's good practice to avoid such situations in your design.

Understanding continuous assignments is vital when designing digital hardware as it allows accurate representation of the continuous and instantaneous flow of signals in your design.