Assertion Coverage

Assertions are a powerful tool used in the design and verification of digital systems to formally verify the behavior of a system. They allow designers to define the intended behavior of a design, and then automatically check that the design's actual behavior matches this intent.

In SystemVerilog, assertions are written using the SystemVerilog Assertion (SVA) language, which is integrated into the SystemVerilog language.

Assertions can be checked dynamically during simulation, and if the behavior defined in the assertion is violated, an error message is generated, helping to identify bugs in the design. In addition to finding bugs, assertions can also be used to collect coverage data, known as assertion coverage.

Assertion Coverage

Assertion coverage is a measure of how well the assertions in a design have been exercised. It tells us how often each assertion has been evaluated and how often it has passed or failed. Assertion coverage is an important part of functional verification as it gives an indication of the extent to which the design's behavior has been checked against its intended behavior.

In SystemVerilog, assertion coverage is typically collected by adding a cover property statement for each assertion. This statement will increment a coverage counter each time the property is proven true.

Here is an example:

property p_valid_data;
  @(posedge clk) disable iff (!reset)
    (valid && ready) |-> ##[1:5] data != 'h0;
endproperty

// Assertion
a_valid_data: assert property (p_valid_data)
  else $error("Data is 'h0 when valid and ready are high");

// Coverage
c_valid_data: cover property (p_valid_data);

In this example, the assert property statement checks that whenever valid and ready are high, the data is not zero within the next 1 to 5 clock cycles. If this property is violated, an error message is printed. The cover property statement will increment a coverage counter each time this property is proven true.

Assertion coverage gives us an insight into which parts of the design's intended behavior have been tested and which have not. It helps identify areas of the design that need more testing and can highlight scenarios that have been missed in the test plan. It is an important part of achieving thorough verification coverage.