Code Coverage

Types of code coverage

Code coverage is a measure used in software testing that describes the degree to which the source code of a program has been tested. It is an important aspect of functional verification and validation processes because it helps identify parts of a system that haven’t been covered by the testbench.

In SystemVerilog, code coverage includes:

1. Line Coverage: This shows which lines of code have been executed during simulation. It’s the simplest form of coverage and can quickly point out sections of code that have not been exercised.

2. Branch (or Conditional) Coverage: This measures whether both the true and false branches of conditional statements like if, case, casez, casex, and unique case have been taken.

3. Toggle Coverage: It measures how many times each bit of a vector has toggled. Toggle coverage is split into 0->1 and 1->0 toggles and can help find stuck-at faults.

4. FSM (Finite State Machine) Coverage: This records transitions between states in FSMs. It is useful for verifying that all valid state transitions have been exercised.

Here's a simple example showing how line and branch coverage would be calculated:

module MyModule;
  initial begin
    if (a == b) begin  // Line 3, Branch Point
      c = a;           // Line 4
    end else begin
      c = b;           // Line 6
    end
  end
endmodule

Here, if a is equal to b, line 4 is executed and we say that the true branch at line 3 has been taken. If a is not equal to b, line 6 is executed and we say that the false branch at line 3 has been taken. Line coverage would report lines 3, 4 and 6 as covered if both the if and else conditions are met during simulation. Branch coverage would report the branch at line 3 as fully covered only if both if and else conditions are met during simulation.

Remember that while code coverage is a valuable tool, it does not guarantee that all possible scenarios are tested, as it's focused on the code itself rather than the specification or requirements of the design.