Inline Constraints

In addition to the constraints that you can define inside a class, SystemVerilog also allows you to specify constraints directly in the randomize() method call. These are called inline constraints.

Inline constraints let you modify the behavior of your constraints on a per-randomization basis. They can be especially useful when you need to override or augment the constraints defined in the class for a specific randomization.

Here's an example of how you can use inline constraints:

class MyClass;
    rand bit [3:0] data;
    constraint data_c { data < 10; }
endclass

MyClass my_obj = new();
my_obj.randomize() with { data < 5; };

In this example, data < 5 is an inline constraint. During the randomization of my_obj, this inline constraint will be used in addition to the constraint data_c defined in the class. This means data will be randomized to a value less than 5, even though the class-level constraint would allow it to be up to 9.

Inline constraints can be as complex as you need them to be. They can also contain implication (->) and logical operators (&&, ||):

my_obj.randomize() with { data < 5; enable -> data == 2; };

In this example, the inline constraints specify that data should be less than 5, and if enable is 1, data should be exactly 2.

One thing to note about inline constraints is that they do not permanently modify the constraints defined in the class. The class constraints will remain the same for the next randomization, unless overridden again by new inline constraints.

Inline constraints give you the flexibility to vary the conditions of randomization as needed, which is crucial when you want to cover different scenarios in your verification environment.