Static Arrays

Fixed-size arrays, also known as static arrays, are the most basic form of arrays in SystemVerilog. The size of a static array is fixed during compile time and cannot be altered during runtime. This means that you must know the number of elements the array will hold before you run the code.

Declaration and Usage

To declare a static array, you need to specify the type of elements it will hold, followed by the name of the array, and then the size or range of indices in square brackets. Here's the basic syntax:

datatype array_name[size]; // For one-dimensional array
datatype array_name[size1][size2]; // For two-dimensional array

For example, to declare a one-dimensional integer array with 10 elements:

integer array1[10];

To declare a two-dimensional real number array with 4x4 elements:

real matrix[4][4];

You can also declare arrays with a specified range, rather than just size:

integer array2[0:9]; // This array has 10 elements, with indices from 0 to 9

To access elements in the array, you use the array name followed by the index of the element in square brackets. Remember, in SystemVerilog, array indices start from 0:

array1[0] = 5; // Sets the first element of array1 to 5

Characteristics and Use Cases

Fixed-size arrays are simple and straightforward to use, making them suitable for situations where you know the size and range of indices in advance. However, their fixed size can be a limitation when you need more flexibility. For example, if you need an array to store a variable number of elements, a dynamic array, an associative array, or a queue might be a more appropriate choice.

That said, fixed-size arrays are often used in design and verification tasks that require storing a fixed number of related data items, such as storing a data packet in a network design or storing the states of a finite state machine.