Memory Operation

Built-in system tasks used for memory operation

Handling memory operations in HDL simulations is vital, especially when dealing with situations such as loading One-Time Programmable (OTP) memory content into the Design Under Test (DUT) during simulation. Tasks like readmemh, readmemb, writememh, and writememb play a pivotal role in such contexts. Let's dive deep into each of these tasks and understand their significance.

Preloading a memory file into OTP using $readmemh or $readmemb

Purpose: Reads data in hexadecimal format from a file, populating the specified memory. This is especially beneficial when you want to initialize a DUT's OTP memory for a simulation run.

Usage:

readmemh("<filename>", memory_name);

Example: Consider a file named data.hex:

2A
4F
B7

And a SystemVerilog code snippet:

reg [7:0] mem [2:0];
initial begin
    readmemh("data.hex", mem);
end

Post-simulation, memory content:

• mem[0] → 2A

• mem[1] → 4F

• mem[2] → B7

Similarly, for $readmemh:

Purpose: Reads data in binary format from a file, populating the specified memory. Useful for initializing OTP or other memory elements with binary data.

Usage:

readmemb("<filename>", memory_name);

Example: Consider a file named data.bin:

10101010
10001111
10110111

And a SystemVerilog code snippet:

reg [7:0] mem [2:0];
initial begin
    readmemb("data.bin", mem);
end

Post-simulation, memory content:

• mem[0] → 10101010 (binary) or AA (hex)

• mem[1] → 10001111 (binary) or 8F (hex)

• mem[2] → 10110111 (binary) or B7 (hex)

Dumping memory content into a file using $writememh or $writememb

$writememh:

Purpose: Outputs memory content as hexadecimal values into a file.

Usage:

writememh("<filename>", memory_name);

Example: Assuming a populated memory:

• mem[0] → 2A

• mem[1] → 4F

• mem[2] → B7

Using writememh("output.hex", mem); will generate output.hex with:

2A
4F
B7

writememb:

Purpose: Outputs memory content as binary values to a file.

Usage:

writememb("<filename>", memory_name);

Example: Assuming a populated memory:

• mem[0] → 10101010 (binary)

• mem[1] → 10001111 (binary)

• mem[2] → 10110111 (binary)

Using writememb("output.bin", mem); will produce output.bin with:

10101010
10001111
10110111

In simple terms, $readmemh, $readmemb, $writememh, and $writememb are tools in SystemVerilog that help us set up and check memory during a test. We can use them to load data into the device's memory at the start of a test. Plus, we can read the memory's contents, change them if needed, and then reload them. This makes it easy to control and understand what's happening with the memory during a simulation.