UVM Register Layer

The UVM Register Layer provides an abstraction of the DUT's registers, allowing them to be accessed in a standard way, regardless of their actual implementation in the DUT.

UVM Register Model

The UVM Register Model is a mirror of the DUT's registers in the testbench. It provides a high-level interface for accessing and manipulating registers, abstracting away the details of the register implementation.

Accessing Registers

With the UVM Register Layer, registers can be accessed using read and write methods. These methods generate sequences that drive the appropriate signals on the DUT interface to perform the register access.

Predictors and Adapters

Predictors and Adapters are used to keep the UVM Register Model synchronized with the actual DUT registers. The Adapter translates between the register transactions and the bus transactions, while the Predictor updates the UVM Register Model based on observed bus transactions.

In the following sections, we'll explore more advanced topics, including how to manage and control the UVM simulation, as well as debugging and resolving issues in a UVM environment.