UVM Phases

UVM provides several predefined phases that help to structure and organize the execution of a testbench. These phases allow for a predictable and orderly execution of the testbench, where each phase has a specific purpose.

Common Phases

Some of the common UVM phases include the build phase, connect phase, end_of_elaboration phase, start_of_simulation phase, run phase, extract phase, and more. Each phase allows different operations, such as object creation, connection setup, simulation execution, and result extraction.

Run-Time Phases

In addition to these common phases, UVM also includes run-time phases, which handle the active operation of the testbench during simulation. The run-time phases include pre_reset, reset, post_reset, pre_configure, configure, post_configure, pre_main, main, post_main, pre_shutdown, and shutdown.

In the next section, we'll delve into more advanced UVM concepts and techniques, including configuration, callbacks, TLM ports, and more.